Conventional semiconductor device manufacturing methods frequently include repeated steps to deposit thin films on semiconductor wafers. In some instances, one or more of these thin films is removed using conventional etching techniques. Such etching techniques may include using a plasma during an etching step to remove a previously deposited thin film(s). Because plasma etch rates may be proportional to a distance between the thin film and a source of the plasma, it is typically advantageous that the distance between the thin film and the plasma source be uniform across an entire wafer containing the thin film thereon. Such uniform distance typically enhances the etching technique by insuring a uniform etch rate and minimizing the amount of thin film residues that are present upon completion of the etching step. Unfortunately, the volume of thin film residues present at the end of an etching step, or upon completion of a sequence of etching steps, may be significant adjacent the edge of the wafer if a profile of the edge causes the distance between a top surface of the wafer and the etching source to vary significantly. This “build-up” in thin film residue at a periphery of the wafer may result in reduced wafer yield if subsequent process steps cause a transfer of thin film particles from the residues to other portions of the top surface of the wafer. For example, a cleaning step that involves passing a cleaning solution laterally across the top and bottom surfaces of the wafer may dislodge particulates from the built-up residues and redeposit these particulates on active portions of the wafer. As will be understood by those skilled in the art, these redeposited particulates may operate as substantial defects on integrated circuit dies that are cut from the wafer at the end of a semiconductor device manufacturing process. Such defects may cause the dies to be discarded as defective during reliability testing.
Conventional techniques have been developed to manufacture semiconductor wafers having asymmetric edge profiles. For example, U.S. Pat. No. 4,630,093 discloses a wafer with an asymmetric peripheral edge with regard to a middle plane of the wafer. This asymmetric peripheral edge is used to denote the front and rear surfaces of the semiconductor wafer. In particular, FIG. 2 of the '093 patent illustrates a wafer having a peripheral edge that is in the shape of a half-round. The radius of curvature of the half-round changes in the direction of thickness. U.S. Pat. Nos. 5,021,862,5,045,505 and 5,110,764 also disclose semiconductor wafers having asymmetric edge profiles. These edge profiles have beveled portions that are formed along circumferential edges of front and back surfaces of the wafers. The circumferential edges are described as preventing chipping during wafer handling. U.S. Pat. Nos. 5,225,235, 5,230,747 and 5,279,992 also disclose wafers having rounded and/or chamfered edges that are utilized to prevent wafer chipping.
Notwithstanding advances in semiconductor wafer processing and the conventional use of semiconductor wafers having asymmetric edge profiles, there continues to be a need for semiconductor wafer manufacturing methods that result in wafers that are less susceptible to processing defects caused by residue formation on wafer edges.